Certified Interoperability: UHF Gen 2 Achieves Another Milestone

By John Schroeter

While the authors of the Gen 2 spec worked to make it as explicit and unambiguous as possible, there remains the opportunity for misinterpretation. What's more, there are a great many variables in any sequence of commands a reader might issue. In fact, given the complexity of options and modes of operation available in Gen 2, there is practically an infinite number of possibilities in the way a reader can communicate with a tag, both in terms of the commands it can send and what it can ask the tag to do.


So what good is conformance testing? Plenty. At minimum, it's a critical filter ensuring that a reader and/or a tag meet the essential aspects of the Gen 2 spec, that products issue the correct wave forms, and that they exhibit the right timing parameters and properly exercise key elements of the protocol. And while a number of products were certified in the first round of submissions, the process actually sent many of them back to the drawing board. As such, earning the conformance certification is an appropriate first hurdle for products to clear. The early availability of certified products also enabled a great many deployment pilots, which was critical to building out and testing the new UHF infrastructure. The fact that interoperability testing is underway now is a significant indicator of the industry's maturity. In short, with multiple Gen 2 products currently available, interoperability testing can pick up where conformance testing left off.

Inside Interoperability
The process of interoperability certification allows EPCglobal to verify the correct operation of tags with a reference reader system, and of readers with a reference tag system. Impinj's Monza tag silicon and Speedway reader were key elements in this reference system, and were the first to receive interoperability certification. The interoperability testing covers the vast majority of cases users can expect to see in the field, providing the assurance that both tags and readers—even those from various manufacturers—will respond properly.

To this end, test suites are created by assembling a group of test cases that exercise the major functionality subsets of the Gen 2 protocol. Four test suites were defined for certification purposes: Select/Inventory, Memory Access, Permalock/Kill and Special (optional). Each test suite is run for a given set of reader-tag air-interface conditions. The set of parameters defining the air-interface settings is called the mode, which establishes both the user-settable reader-to-tag characteristics (data rates, modulation schemes, etc.), and the tag-to-reader characteristics.

What's Next?

Clearly, certified UHF Gen 2 interoperability is a major milestone in the development of RFID systems. As important as that is, though, performance is still what matters most to RFID deployments. RFID hardware must have a high degree of receptivity, meaning both tags and readers are not only extremely sensitive to each other's signals, they are also able to reject the interference from other RF sources operating in the area.

EPCglobal, recognizing the critical importance of receptivity to system performance, created a working group to address these and other issues. In the process of defining minimum requirements, they'll address not only the performance of tags applied to various classes of products—such RF-friendly materials as paper, plastic, wood and so forth, as well as more problematic materials such as liquids and metals—but also the key aspects of tag performance: sensitivity, interference rejection, orientation, electrostatic discharge (ESD) and others parameters. Once the objectives are defined, the EPCglobal Hardware Action Group will draft the specifications for performance testing. This will complete the promise outlined by the framers of the UHF Gen 2 standard.

John Schroeter is senior marketing communications manager at Impinj, a Seattle-based provider of Gen 2 RFID chips and technology. Prior to joining Impinj, Schroeter held marketing management posts at UTMC, Seattle Silicon and Fairchild Semiconductor's memory and high-speed logic division. He is the author of the Prentice Hall book Surviving the ASIC Experience.